In FIG. 2, there is shown an equivalent circuit of a memory cell for an SRAM arranged by two high resistance loads and four transistor cells. This memory cell is constructed as a flip-flop circuit. In the flip-flop circuit, a pair of inverter transistors Q1 and Q2 are connected to load resistors R1 and R2 at respective nodes 30 and 31, and the load resistors R1 and R2 are connected via nodes 32 and 33, respectively, to a power supply voltage line "Vcc". A data communication with an external circuit of this memory cell is carried out by way of gate transistors Q3 and Q4 connected at the nodes 30 and 31. In this figure, symbol "WL" shows a word line, whereas symbols BL and BL' denote bit lines.
Although there is another type of SRAM using 6 transistor cells by replacing load transistors for the load resistors R1 and R2 shown in FIG. 2, the 4-transistor cell structure using a high resistance load becomes more popular, in which the thin film wiring made of high-resistance polysilicon is employed as the load resistors, as shown in FIG. 2, to reduce the cell area.
FIG. 3 is a schematic sectional view of the conventional structure of a portion of the above-described nodes 30 and 31. As represented in this figure, a high-resistance polysilicon thin film 103 constituting the load resistor R1 or R2 is formed on an inter-layer insulating film 102 fabricated on a silicon substrate 101. This high-resistance thin polysilicon film 103 is connected to a metal wiring 105 formed on this thin polysilicon film via a contact hole 106 formed in an inter-layer insulating film 104 formed on the polysilicon thin film.
As shown in the figure, according to this conventional structure, the contact hole 106 is formed to penetrate only the inter-layer insulating film 104, and also the electric connection between the high-resistance polysilicon thin film 103 and the metal wiring 105 is achieved such that the metal wiring 105 is in contact with the entire surface of the polysilicon thin film exposed to a bottom of the contact hole 106.
On the other hand, in the above-described 4-transistor cell using the high-resistance load, very recently, a demand to increase more and more the resistance value of its load resistance portion becomes larger with the need to achieve high integration and low power consumption. However, there is a limitation in decreasing the thickness of the polysilicon film, which constitutes the load resistance, due to a reliability of the load resistor. On the other hand, there is another practical limitation in reducing the size of the semiconductor device in view of integration.